Verification
Verification
We have the one of the strongest team in DV. Our team can execute verification from scratch of complex SoC’s and IP’s by using latest methodologies such as SV-UVM, UPF and meeting key KPI such as 100% functional and code coverage.
RTL design
RTL design
Our designers are experts in all aspects of SOC design, starting at architecture specifications, through RTL design, verification, physical design - all the way to tapeout and post-silicon bringup/debug. Xeedo Design can help design and implement your low power, high speed, area efficient designs, in the most advanced process technologies.
Physical Design
Physical Design
We provide support throughout RTL to GDSII stages of ASIC development flow. Our experienced team has developed advanced flows for power aware synthesis (UPF, CPF), timing constraint generation (STA), netlist floor planning for best possible PPA and place and route(PNR) for overcoming ever increasing complexity. Our engineers in-depth knowledge of EDA tools and scripting skills enable us to deliver full turn-key ASIC development.
Analog Layout
Analog Layout
Our team is expert in taking care of custom full chip analog layout design, including I/O layout for various technologies and foundry interface.
DFT
DFT
With rising mission critical application and competition, inserting testing capability in the design stage of the chip is ever so important. Our team have expertise in developing and integrating a complete test strategy for your ASIC design to deliver high fault coverage.